1. The Boundary Scan Standard
IEEE/ANSI Standard 1149.1-1990, entitled “Standard Test Access Port and Boundary Scan Architecture,” is incorporated by reference here and describes a testing scheme using “scan registers” to capture data from the input and output pins of an electronic device. The term “register” broadly refers to groups of digital logic storage units that are read or written as a unit. For example, a simple register may be constructed from a group of “flip-flops” whose outputs toggle simultaneously in response to a “clock” timing signal. In another type of register, called a “shift register,” stored values can also be circulated between the storage elements in the register when a particular control signal is pulsed. Scan registers act like a group of flip-flops until they are switched into a test mode where they become one long shift register. This configuration allows scan register data to be captured in parallel and shifted serially between storage elements in the scan register. A detailed discussion of boundary scan testing and scan registers is provided in “The Boundary-Scan Handbook” by Kenneth P. Parker (Kluwer Academic Publishers, 2d edition) and “Agilent 3070 Family Boundary-Scan Fundamentals H7230A Opt 210 (E3795C)” (Agilent Technologies), both of which are also incorporated by reference here in their entirety. Testing systems that use boundary scan technology in order to facilitate integrated circuit testing, board testing, and/or system level testing are also commercially-available from a variety of vendors including Agilent Technologies Inc.; Corelis, Inc.; ASSET InterTech, Inc.; JTAG Technologies B.V., Goepel Electronics; Teredyne Inc.; Agere Systems; Sightsys LTD.; Intellitech Corp.; Acugen Software; and others.
As shown in FIG. 1, the basic architecture for implementing boundary scan testing is provided on an integrated circuit 100 (or other device) by four (or, optionally, five) package pins forming the Test Access Port (“TAP”). The TAP is used for communicating with on-chip, boundary scan logic using a testing unit (such as Agilent Technologies' “3070 Series 3” in-circuit test system), or other device, to send and receive various signals via the TAP. The logic for the TAP includes a finite state machine, called the “TAP controller,” that is driven by signals applied to the Test Clock (“TCK”), Test Mode Select (“TMS”), and optional Test Reset (“TRST”) pins. The remaining two pins, Test Data In (“TDI”) and Test Data Out (“TDO”), are used for serially shifting data into and out of registers as discussed below.
The registers in the boundary scan logic include at least two data registers (“DR”) and an instruction register (“IR”). The “boundary (data) register” 102 is a scan register that is used to control and observe activities on the input and output pins of the integrated circuit 100 or other device. The boundary register 102 is formed by “boundary register cells” 104 disposed between each of the terminals 106 and the internal logic 108 of the integrated circuit 100 (but not the TAP pins). Each cell typically includes a shift register “capture” flip-flop and a parallel “update” flip-flop or latch. The serial inputs and outputs for each cell are connected to form a serial shift path, or “scan path,” 110 through the boundary scan cells 104. For input pins 106A on the integrated circuit 100, the parallel inputs and outputs of the boundary register 102 are connected to the device pin and system circuitry, respectively. For output pins 106B, these assignments are reversed.
The second data register in the boundary scan logic is the “bypass register” 112. The bypass register 112 provides a one-bit shift path through the integrated circuit that can be used to shorten the length of the system scan path in a boundary scan chain, as described in more detail below with regard to FIG. 2.
The instruction register (“IR”) 114 defines the mode in which the data registers operate. Similar to the data registers 110 and 112, the instruction register 114 also includes cells with a shift register “capture” flip-flop and a parallel “update” flip-flop or latch. Once the instruction register is connected between TDI and TDO, the shift register portion holds new instruction bits moving through the register while the output latches hold the “active” instruction in place while any shifting is done (in order to prevent “shift ripple”). The active instruction is then decoded and used to set the operational mode where a selected, or “target,” data register is placed between TDO and TDI.
As mentioned above, the Boundary-Scan Standard also allows the scan paths 110 of multiple integrated circuits 100, and/or other devices having the boundary scan architecture shown in FIG. 1, to be linked together (and with other devices that do not include the boundary scan architecture 100) at the system level. For example, as illustrated by the system 200 shown in FIG. 2, the TDI pin (FIG. 1) of each of the boundary scan devices 230, 240, 250, 260 and 270 is linked to the TDO pin (FIG. 1) of the preceding device in the scan path chain 210. The TDI pin of the first device 220 receives a serial input signal from the testing unit (not shown), or other device, while the TDO pin of the last device 270 in the chain 210 provides an output signal to the testing unit or other device.
FIG. 3 is a state diagram 300 for the TAP controller (or “controller”) 118 shown in FIG. 1 according to the Boundary Scan Standard. In FIG. 3, each of the sixteen states of the controller 118 is labeled with a name, and the arc between states is shown with a 0 or 1 to indicate the logic value of the TMS signal that must be set before the rising edge of the next TCK (“clock”) pulse in order to cause the transition the controller to the next state. The TEST-LOGIC-RESET state is entered on power-up of the device 100 (FIG. 1) and disables the boundary scan control logic so that the integrated circuit, or other device, will operate normally. The RUN-TEST/IDLE state is then entered when TMS is (a logical) low and the controller 118 remains in this state as long as TMS is low. The remaining states are arranged in two vertical columns with the data column (on the left) referencing the targeted data registers (“DR”) 102 and the instruction column (on the right) referencing the instruction register (“IR”) 114.
When the TAP controller 118 is in the RUN-TEST/IDLE state and TMS goes high, the controller enters the SELECT-DR-SCAN state on the next (rising edge of TCK) clock pulse. This is a temporary controller state that is exited on the next rising edge of TCK. If TMS is held low on the next (rising edge of TCK) clock pulse, then the controller 118 goes into the CAPTURE-DR state in the data column, and a scan sequence is initiated for the selected test data register.
If TMS is kept high during the SELECT-DR-SCAN state, then, on the next clock pulse, the controller 118 moves into the first state in the instruction column, SELECT-IR-SCAN. This is also a temporary state where a decision is made whether to either continue in the instruction column or reset the controller by returning to the TEST-LOGIC/RESET state. If TMS is held low during the SELECT-IR-SCAN state, then the controller 118 moves into the CAPTURE-IR state on the next clock pulse and a scan sequence is initiated for the instruction register 114.
More specifically, during the CAPTURE-IR state, the shift register portion of the instruction register 114 parallel loads a pattern of fixed logic values on the rising edge of TCK. The TAP controller 118 then either enters the SHIFT-IR state if TMS is low, or the EXIT-IR state if TMS is high.
In the SHIFT-IR state, the instruction register 114 is connected between TDI and TDO and the captured pattern is shifted one stage toward the serial input for the rising edge of each clock pulse while TMS is low. Simultaneously, new instruction bits are shifted out of the instruction register 114 to TDI during the falling edge of each clock pulse. The EXIT-IR state is then entered when TMS goes high and is simply another temporary controller state in which a decision is made whether to enter the PAUSE-IR or UPDATE-IR state.
In the PAUSE-IR state, the TAP controller 118 allows the shifting of the instruction register 114 to be temporarily halted, typically in order to accommodate the slower speed of other test equipment. The controller 118 remains in this state while TMS is low and then moves to EXIT2-IR on the next rising edge of TCK when TMS high. EXIT2-IR is another temporary controller state for determining whether to return to the SHIFT-IR state, or move on to the UPDATE-IR state.
In the UPDATE-IR state, the instruction that was previously shifted into the instruction register 114 is latched, on the falling edge of TCK, into the hold portion of the instruction register. Once the new instruction has been latched, it becomes the “current instruction” and sets a new operational mode. From this state, the controller 118 can then enter the SELECT-DR-SCAN state if TMS is high, or the RUN-TEST/IDLE state if TMS is low. The remaining states for the data register column are similar to those for the instruction register column.
For example, during the UPDATE-DR state, a response pattern (sometimes referred to as “vector” data) is latched on the falling edge of TCK from the shift register onto the parallel outputs of the targeted data register that is set by the current instruction. The BYPASS instruction (all 1s in the instruction register) places the single-bit bypass data register 112 between TDI and TDO in order to provide a short path through the component. The EXTEST instruction (with a pattern that is left to the circuit designer), on the other hand, targets the boundary register 102 between TDI and TDO so that, during the SHIFT-DR state, vector data is shifted in (on the rising edge of TCK) and out (on the falling edge of TCK) of the boundary registers 102 while TMS remains low. The new data is then latched into the parallel outputs of the boundary register 102 on the falling edge of TCK during the UPDATE-DR state.
2. Ground Bounce During Boundary Scan
Certain boundary scan tests are known to be particularly susceptible to ground bounce, as discussed in “In-Circuit Boundary Scan Connection Test Ground Bounce: A Case Study In Prevention & Cures,” presented at the NepConWest 2000 Symposium by Raymond Balzar and Philip King; “Ground Bounce Basics and Best Practice,” by Phil King available from Agilent Technologies; and U.S. Pat. Nos. 6,000,050 and 6,243,843; all of which are incorporated by reference here in their entirety. In general terms, ground bounce is a transient voltage difference between the ground reference points in two parts of a circuit. This typically occurs when current through an impedance (typically, an inductance and/or resistance) in the power distribution pathway creates a voltage drop across internal circuit nodes that are supposed to have the same voltage value (typically, power or ground). For board testing, this voltage differential usually arises between the test system ground and the device under test. However, ground bounce may also occur during integrated circuit level, or system level, testing.
Ground bounce can be minimized through proper integrated circuit design, board layout, and tester to board/system connections. There are also other approaches that attempt to mitigate the effects of ground bounce once they occur. These latter approaches typically alter the boundary scan test pattern in an attempt to minimize or optimize simultaneous pin transitions by 1) arranging the timing of when it occurs to be at a “safe” point in the test sequence; 2) using the TAP state diagram to trap the controller at one state; 3) wiring the test fixture in such a way that the ground bounce is minimized for the TCK, TMS and TRST pins; and 4) using a controlled slew rate on TCK to mask the ground bounce.
Ground bounce typically manifested itself as a superimposed voltage fluctuation in a signal which can sometimes be measured using conventional techniques. If that signal is TCK, and the fluctuation is large enough to inject a new clock cycle, then the bounce can cause loss of synchronization with the expected TAP controller state shown in FIG. 1. Inductive ground bounce is particularly problematic in this regard due to the current surges created as large numbers of drivers change state simultaneously and is expected to occur most often on the falling edge of TCK while in either of the UPDATE-IR or UPDATE-DR (“UPDATE”) states, particularly when in, or going out of, the EXTEST mode. A single boundary scan test operation will often have many such UPDATE events and corresponding opportunities for ground bounce.
Ground bounce that causes an extra TCK pulse during an UPDATE state can be recognized, under certain conditions, by examining the target bits that are shifted and noting an instruction register capture pattern, rather than the normally expected target bit pattern. Under other conditions, ground bounce can also be inferred from a disabling of the TDO pin during a shift state. Yet another ground bounce detection scheme is discussed in U.S. Pat. No. 6,243,843. However, when improper boundary scan test results are obtained, a ground bounce problem is more often presumed to be one of many possible causes and the test is simply rerun while implementing a ground bounce suppression algorithm. Of course, if ground bounce is anticipated, then a ground bounce suppression algorithm may be applied from the start of the test.
One conventional ground bounce suppression algorithm involves holding TMS low before the falling edge of TCK while in the UPDATE-DR and/or UPDATE-IR states. A spurious TCK pulse at the falling edge of TCK will therefore cause the TAP controller to go into the RUN-TEST/IDLE state where it will remain, during any further ground-bounce-induced clock pulses, until TMS is made high. After waiting a suitable period of time (i.e., number of clock pulses) for the effects of any such ground bounce to dissipate, the test can then be continued with the same input sequence. Thus, if a ground bounce induces multiple clock pulses during the transition from one of the UPDATE states, and TMS is held low, the controller 118 can be “trapped” in the RUN-TEST/IDLE state until the effects of the ground bounce on TCK have dissipated and the test can be continued.
However, this trap will not be successful if the ground bounce also causes the TMS line to appear to the controller 118 as a logical 1 at the time of the spurious clock signal. In that case, the TAP controller 118 will move to another state where it will not be trapped, regardless of whether TMS is kept low. Furthermore, the input bit pattern sequence that was applied to the TAP pins when TMS moved high is unlikely to be synchronized with, or appropriate for, the state of the TAP controller induced by the ground bounce when the test continues.